International Journal of Engineering Research in Electrical and Electronic Engineering(IJEREEE)

Monthly Journal for Electrical and Electronic Engineering

International Journal of Engineering Research in Electrical and Electronic Engineering

Volume2 ,November 2015.

Volume2,November 2015,

Topic : COMPARISON OF POWER IN CMOS AND ADIABATIC FULL ADDER CIRCUITS USING 0.18µM TECHNOLOGY PARAMETERS

Authors:Neha Sharan || Mandavi Gahlot

Abstract:This paper presents the design and power comparison of charge-recovering adiabatic full adder circuits and CMOS logic based full adder circuit. The low-voltage Adiabatic Logic circuits have been designed for low-voltage, low-power dissipation and high-frequency operation. A comparative analysis was performed in which logic gates were constructed using adiabatic logic. A layout-based simulation was then performed to verify the operation. Simulation results have shown that the adiabatic logic family is suitable for low voltage operation below 0.18?m CMOS technology. Full adder circuitries are vital mechanisms in applications such as micro processors and microcontrollers. Along with the fundamental addition, full adders are used in performing other useful arithmetic operations such as multiplication, division, subtraction, address calculation, etc. In this paper conservative complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits (PFAL, TGAL) are characterized in terms of leakage power, process variations, temperature variations and transistor count using 0.18?m CMOS technology..

Keywords: Adiabatic Switching, CMOS technology, Static power dissipation, Transmission Gates

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DOI: 01.1617/vol1iss8pid033


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Editor-in-Chief
Dr.Krzysztof Chwastek
Associate Professor,
Czestochowa University of Technology, Polland.


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IMPACT FACTOR: 3.784

ISSN(Online): 2395-2717

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