Author : Suhas B Shirol 1
Date of Publication :7th August 2017
Abstract: In recent years, the technology is changing faster than the Moore's law stated hence to develop the devices which are efficient with respect to power, area and speed has become a challenge in field of VLSI. The main focus of this paper is comparative study of Low Power Transition, Low Area and High Fault Coverage in BIST architectures, it has been seen that during test power consumed is higher due to transition activity, area overhead is more and fault coverage is less for CUT.
Reference :
-
- Sunghoon Chun, Taejin Kim and Sungho Kang, "A New Low Energy BIST Using A Statistical Code," IEEE, pp. 647-652, 2008
- Lubna Naim and Tarana A. Chandel, “Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications,” International Journal of Computer Applications., vol. 87, no. 15, February 2014.
- Abu-Issa and S. Quigley, Bit-swapping LFSR and scan-chain ordering: A novel technique for peak- and average-power reduction in scan-based BIST, IEEE Trans. Compute.- Aided Design Integral. Circuits Syst., vol. 28, no. 5, pp. 755–759, May 2009.
- Mehrdad Nourani, Mohammad Tehranipoor and Nisar Ahmed, “Low- Transition Test Pattern Generation for BIST-Based Applications,” IEEE Transactions on Computers., vol. 57, no. 3, pp. 303-315, March 2008.
- Praveen J, and M N Shanmukhaswamy, “Power Reduction Technique in LFSR using Modified Control Logic for VLSI Circuit,” International Conference on Electronic Design and Signal Processing (ICEDSP) 2012.
- Miroslaw Puczko, " Low power Test Pattern Generator for BIST ", European Union, 2015
- K. Murali Krishna and M. Sailaja, "Low Power Memory BIST Address Generator Using Clock Controlled LFSR", IEEE WiSPNET 2016.