Author : Suhas B Shirol 1
Date of Publication :7th August 2017
Abstract: In recent years, the technology is changing faster than the Moore's law stated hence to develop the devices which are efficient with respect to power, area and speed has become a challenge in field of VLSI. The main focus of this paper is comparative study of Low Power Transition, Low Area and High Fault Coverage in BIST architectures, it has been seen that during test power consumed is higher due to transition activity, area overhead is more and fault coverage is less for CUT.
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