Author : Amar Patil 1
Date of Publication :7th August 2017
Abstract: As the technology is being scaled down leakage power is becoming an important contributing factor in total power dissipation in the circuit. So in the portable devices such as cell phones, laptops emphasis has to be given to reduce power consumption during active as well as standby mode. This paper presents the Design of LDO voltage regulator. This work aims at further reduction in power consumption and drop out voltage using Floating gate pass transistor. A comparison of different Low Drop out regulator using various pass transistor logic is proposed and the Designed LDO shows a reduction of drop out voltage of 15.38% in the circuit. This circuit is simulated in 180nm CMOS Technology.
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