Open Access Journal

ISSN : 2395-2717 (Online)

International Journal of Engineering Research in Computer Science and Engineering (IJERCSE)

Monthly Journal for Computer Science and Engineering

Open Access Journal

International Journal of Engineering Research in Electrical and Electronic Engineering(IJEREEE)

Monthly Journal for Electrical and Electronic Engineering

ISSN : 2395-2717 (Online)

Design of Low Drop Out voltage regulator for low power applications

Author : Amar Patil 1 S L Gangadharaiah 2

Date of Publication :7th August 2017

Abstract: As the technology is being scaled down leakage power is becoming an important contributing factor in total power dissipation in the circuit. So in the portable devices such as cell phones, laptops emphasis has to be given to reduce power consumption during active as well as standby mode. This paper presents the Design of LDO voltage regulator. This work aims at further reduction in power consumption and drop out voltage using Floating gate pass transistor. A comparison of different Low Drop out regulator using various pass transistor logic is proposed and the Designed LDO shows a reduction of drop out voltage of 15.38% in the circuit. This circuit is simulated in 180nm CMOS Technology.

Reference :

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    2. S. S. Chong and P. K. Chan, “A 0.9-uA quiescent current output-capacitorless LDO regulator with adaptive power transistors in 65-nm CMOS,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 60, no. 4, pp. 1072– 1081, 2013.
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    4.  Y. I. Kim and S. S. Lee, “A capacitorless LDO regulator with fast feedback technique and low-quiescent current error amplifier,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 60, no. 6, pp. 326–330, 2013.
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