Author : Darshan R S 1
Date of Publication :14th August 2017
Abstract: As the technology is being scaled down leakage power is becoming an important contributing factor in total power dissipation of the circuit. So in the portable electronic devices such as cell phones, laptops emphasis has to be given to reduce power consumption during active as well as standby mode. This paper presents a Schmitt-triggerbased 12T SRAM cell which consumes lowest average power as well as lowest leakage power among the cells considered for comparison. The results have been obtained using Cadence Virtuoso Tool with 180nm Technology. The layout is drawn in 180nm technology to layout versus schematic for the proposed 12T SRAM cell
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