Author : M.M.Samreen 1
Date of Publication :30th November 2017
Abstract: A Reliable low-power and fast accelerated multiplier is implemented by using a redundant fault tolerant technique, “Input Output Logic Based”(IOLB) ,this technique is implemented in the fast accelerated dada multiplier is proposed by implementing two algorithms i.e. partial products are obtained in to two parts and integration of a designed hybrid final adder with dada multiplier and obtained partial products are also implemented by using array based multiplier ,tradeoffs between these two multipliers are compared with and without IOLB logic by using the fault tolerant technique power of the multiplier is reduced to 31.1 %, area overhead of the gates required in the multiplier is 23.2% ,speed of the multiplier is increased to 40.1%.
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