Author : V.N. Mahawadiwar 1
Date of Publication :28th March 2018
Abstract: This paper proposes the analysis & implementation of FIR Filter using low power adder and multipliers. The everincreasing market segment of portable electronics devices demands the availability of low power building blocks. With the explosive growth in Laptops, portable personal communication systems and evaluation of the shrinking technology and flexible circuits, the efforts in low power microelectronics have been identified. In this scheme, the function of the adder is minimized by a technique called scaling and rounding-off Filter coefficient and truncation of unnecessary bits in order to reduce the power consumption of FIR Filter. Evaluation of power, area, and speed for different types of adders and multipliers is carried out and the FIR filter is designed with the optimized combination of adders and multipliers for low power and high-speed application. The Full Adder designed with multiplexers do not exhibit any leakage problems and short circuits problems. The current trend towards low-power design is mainly driven by two forces, the growing demand for long-life autonomous portable equipment and the technological limitations of high-performance VLSI systems. The proposed Design of High-Speed FIR Filter for DSP Application with Optimized Adder & Multiplier is simulated using Active HDL and implemented using Tanner tool.
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