Date of Publication :May 2026

Abstract: The XOR and XNOR gates are one of the most commonly utilized functions in digital arithmetic circuits such as full adders, subtractors, compressors, multipliers, parity generators, comparators, and arithmetic logic units. Given the wide-ranging application of these arithmetic functions, the efficiency of XOR-XNOR circuits plays a crucial role in determining power consumption, delay, power-delay product, area, output swing, and driving capability. For decades, XOR-XNOR circuits have moved from conventional static CMOS circuits to pass-transistor logic, transmission-gate logic, complementary pass-transistor logic, double-pass-transistor logic, gate diffusion input logic, dynamic logic, and hybrid logic designs. In more recent years, FinFET-based circuits have gained popularity due to their superior electrostatic characteristics and lower leakage current at nanoscale technology levels. This review article will systematically present an analysis of XOR-XNOR circuits using both CMOS and FinFET device models. A detailed focus will be placed on XOR-XNOR generation using either a single circuit or dual circuits to generate XOR and XNOR simultaneously for low-power applications. It will be observed that even though many circuits exist in literature that provide some benefits such as reduced transistor count, leakage current, delay, and power consumption, various issues persist, such as threshold voltage loss, weak output swing, unbalanced delay of XOR and XNOR outputs, leakage current in CMOS devices, and lack of verification beyond full adder circuits. This research proposes an interesting research problem involving FinFET-based simultaneous XOR-XNOR generation and further evaluation in multipliers and image processors.

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