1. 1. I-chyn Wey,Chien-Chang Peng, and Feng-Yu Liao “Reliable Low-power Multiplier Design Using Fixed Width Replica Redundancy Block” IEEE trans,Very Large Scale Integr.(VLSI) syst vol 23 No 1 .
   2. E. E. Swartzlander, Jr. and G. Goto, "Computer arithmetic," The Computer Engineering Handbook, V. G. Oklobdzija, ed., Boca Raton, FL: CRC Press, 2002.
   3. C. S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Transactions on Electronic Computers, Vol. EC-13, pp. 14-17, 1964.
   4. Luigi Dadda, “Some Schemes for Parallel Multipliers,” Alta Frequenza, Vol. 34, pp. 349-356, August 1965
   5. K.C. Bickerstaff, E.E. Swartzlander, M.J. Schulte, Analysis of column compression multipliers, Proceedings of 15th IEEE Symposium on Computer Arithmeitc,2001.
   6. W. J. Townsend, Earl E. Swartzlander and J.A. Abraham, “A comparison of Dadda and Wallace multiplier delays”, Advanced Signal Processing Algorithms, Architectures and Implementations XIII. Proceedings of the SPIE, vol. 5205, 2003, pages 552- 560 7.
   7. B. Shim, S. Sridhara, and N. R. Shanbhag, “Reliable low-power digitalsignal processing via reduced precision redundancy,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 497–510,May 2004.